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4.5.1
SPI Error
The following SPI conditions result in a SPI error:
? SCLK is high when CS is asserted the number of SCLK rising edges detected while CS is asserted is not equal
to 16
? SCLK is high when CS is negated
? Command message parity error (MOSI)
? Bit 15 of Acceleration Data Request is not equal to ‘0’
? Bits 3 through 11 of an Acceleration Request are not equal to ‘0’
? Bits 0 through 7 of a Register Read Request are not equal to ‘0’
MMA68xx responds to a SPI error with a “SPI Error” response as shown in Table 30 . This applies to both acceleration data
request SPI errors, and Register Access SPI errors.
The arming function will not be updated if a SPI Error is detected. The PCM output is not affected by a SPI Error.
4.5.2
SPI Data Output Verification Error
MMA68xx includes a function to verify the integrity of the data output to the MISO pin. The function reads the data transmitted
on the MISO pin and compares it against the data intended to be transmitted. If any one bit doesn’t match, a SPI MISO Mismatch
Fault is detected and the MISOERR flag in the DEVSTAT register is set.
If a valid SPI acceleration request message is received during the SPI transfer with the MISO mismatch failure, the SPI accel-
eration request message is ignored and MMA68xx responds with a “MISO Error” response during the subsequent SPI message
(reference Table 30 ). The Arming function is not updated if a MISO mismatch failure occurs. The PCM function is not affected by
the MISO mismatch failure.
If a valid SPI register write request message is received during the SPI transfer with the MISO mismatch failure, the register
write is completed as requested, but MMA68xx responds with a “MISO Error” response as shown in Table 30 , during the subse-
quent SPI message.
If a valid SPI register read request message is received during the SPI transfer with the MISO mismatch failure, the register
read is ignored and MMA68xx responds with a “MISO Error” response as shown in Table 30 , during the subsequent SPI mes-
sage. If the register read request is for the DEVSTAT register, the DEVSTAT register will not be cleared.
In all cases, the MISOERR flag in the DEVSTAT register will remain set until a successful SPI Register Read Request of the
DEVSTAT register is completed.
SPI DATA OUT SHIFT REGISTER
DATA OUT BUFFER
D
Q
D
Q
MISO
R
SCLK
Figure 34. SPI Data Output Verification
4.5.3
Invalid Requests
4.5.3.1
Acceleration Data Request Mismatch Failure
D
R
Q
MISO ERR
MMA68xx detects an “Acceleration Data Request Mismatch” error if the SPI “Acceleration Data Request” Command data listed
in Table 32 does not match the internal register settings. MMA68xx responds to an “Acceleration Data Request Mismatch” error
with an “Invalid Accel Request” response as specified in Table 30 on the subsequent SPI message only. No internal fault is re-
corded. The arming function will not be updated if an “Acceleration Data Request Mismatch” Error is detected. The PCM output
is not affected by the “Acceleration Data Request Mismatch” error.
Register operations will be executed as specified in Section 4.4 .
MMA68xx
Sensors
Freescale Semiconductor, Inc.
49
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